1. Field of the Invention
The present invention relates to a fabrication method of a capacitor for a semiconductor memory cell, and more particularly, relates to fabrication method of a twin-tub capacitor for a DRAM (Dynamic Random Access Memory) cell.
2. Description of the Related Art
As the dimensions of semiconductor devices are being scaled down to a deep sub-micron level, the size of the capacitor in a DRAM cell is also being reduced. Since the capacitance is proportional to the surface area of the capacitor, as the area of a memory cell decreases, the capacitance of the capacitor tends to decrease, thereby lowering the performance of the memory cells. On the other hand, the advances in computer applications have increased the demand for high capacity memory chips. Thus, the demand of decreasing the size of the memory cells while simultaneously increasing the memory chip capacity has altered the direction of the advancements of the fabrication of a DRAM memory cell capacitor.
For a semiconductor memory cell capacitor, reducing the dielectric layer thickness, substituting with high dielectric constant materials and increasing the capacitor surface area are the three methods generally used to increase a cell capacitance. Among the three methods, reducing the dielectric layer thickness and increasing the dielectric constant pose technical challenges, especially in mass productions where the reliability of the device and the yield risks may be affected. Thus, increasing the surface area of a capacitor is the preferred approach to increase the capacitance in a limited cell size.
Currently, the surface area of a capacitor is increased by means of the hemispherical grain (HSG) technology or changing the capacitor surface. The HSG process is popular and widely used in the semiconductor field; however, the equipment for the process is more expensive compared to the traditional low pressure chemical vapor deposition (LPCVD) furnace. Furthermore, the HSG growth process is complicated and vulnerable to variations, compared to changing the capacitor structure, which is simple and easy to manipulate.
FIGS. 1A to 1C are cross-sectional views of the conventional stack, crown and twin-tub capacitors.
According to FIGS. 1A to 1C, the stack 100 and crown 102 capacitors are the two most frequently used structures for a DRAM cell application. Between these two capacitors, the crown capacitor 102 is preferred because of the extra surface area from its inner wall.
The more advanced twin-tub capacitor 104 comprises even more inner walls than that of the crown capacitor 102. Hence, the twin-tub capacitor 104 has the most surface areas among the three types of capacitor, and is the most appropriate type of capacitor to meet the current trend of having a high capacity memory with a reduced cell size.
Related activities in the manufacturing of a twin-tub capacitor can be referred to U.S. Pat. Nos. 5,652,165 and 5,721,154.